Hardware Engineer interview questions

I partition it around stable functional, power, bandwidth, and service boundaries rather than around schematic size.

• I keep tightly coupled devices together when crossing a connector would consume timing margin, pins, or power integrity margin.
• I separate noisy power or high-current loads from sensitive analog and clocking when that creates a cleaner return-current and thermal design.
• I make replaceable or fast-changing functions separate FRUs only when the connector cost and added failure points are justified by service or reuse.
• I define every cross-board interface with ownership, startup state, bandwidth, latency, power-off behavior, and fault behavior before freezing the split.

For a scalable chassis, I usually start with a switched star and add a second independent star only when the availability requirement justifies its cost.

• A star gives each slot a dedicated channel and contains many link faults to one slot, although the central switch remains a shared fault domain; a multidrop bus fits only low aggregate bandwidth and controlled stub loading.
• I size lane count and contact fields for the maximum required slot bandwidth, management, power, grounds and credible growth rather than the first product configuration.
• I prefer a passive backplane when practical because it is easier to cool and replace, but I verify that its resulting channel length still closes the link budget.
• The connector plan includes keying, staged contacts, slot identification, spare contacts and enough ground pins to preserve return paths for every fabric lane.

I choose the standard whose transaction model already matches the system, and I use a custom SerDes protocol only when PCIe and Ethernet both miss a hard requirement.

• PCIe fits low-latency host-to-device access and a controlled chassis topology, but enumeration, reference clocks, reach, and hot-plug need system-level ownership.
• Ethernet fits routable many-to-many traffic, longer reach, and vendor interoperability, at the cost of packet overhead and less deterministic latency.
• A custom fabric can minimize latency or carry application-specific framing, but it makes us own link training, error recovery, diagnostics, verification, and long-term FPGA or ASIC support.
• I compare usable bandwidth, latency, fault recovery, software ecosystem, power per bit, connector reach, and qualification cost before deciding.

I define the compliance planes, start from the protocol-defined channel metric and receiver tolerance, and allocate loss and reflection budget across the elements included between those planes.

• I evaluate insertion loss at the protocol Nyquist frequency and beyond, plus return loss, insertion-loss deviation and resonances that a single decibel figure hides.
• I cascade vendor or measured multiport S-parameters in the physical topology, including package or connector breakout vias and unused connector stubs, then run the protocol's statistical or time-domain model.
• I reserve margin for fabrication spread, connector aging, temperature and model uncertainty instead of consuming the full nominal limit.
• Before release, I correlate the model with impedance coupons, a representative transition and de-embedded VNA or TDR measurements.

I distribute only truly common references globally and let each board enter and leave a safe state locally under a defined system protocol.

• Global clocks use controlled differential routes, defined termination and one fanout-buffer output per load rather than long multidrop stubs.
• Reset assertion may be asynchronous, but deassertion is synchronized in every destination clock domain to avoid metastability and recovery or removal violations.
• Power-good is qualified locally and reported to the system controller with timeouts, while critical shutdown still works if firmware or the management bus fails.
• Every slow shared sideband has a defined pull-up owner, voltage-domain isolation, unpowered tolerance and protection against one card holding the bus low.

I give each line card a local hot-swap stage that manages contact sequencing, limits inrush current and enables the main loads only after the input is stable.

• Staggered pins connect protective ground first; the precharge, main-power, management and presence sequence follows the connector and controller architecture, with an enable or interlock contact preventing load turn-on until power contacts are fully mated.
• The hot-swap controller, MOSFET safe operating area, current limit and timer are sized from card capacitance, worst input voltage, source impedance and allowed backplane droop.
• Precharge or a controlled current ramp keeps neighboring slots alive, while an eFuse or breaker isolates a short without firmware participation.
• Removal includes load shutdown, stored-energy discharge and connector-arc control so the card and contacts remain within rating.

I derive fault domains from the required service continuity, then make redundant paths independent enough that one physical failure cannot remove both.

• Compute, fabric, power, cooling, and management are mapped separately because two redundant CPUs still share a failure if they use one clock, backplane switch, or fuse.
• Dual feeds use independent protection and controlled ORing so a short or powered-down source cannot backfeed the healthy path.
• Board boundaries include isolation for sidebands, resets, and shared buses, since a stuck-low management line can otherwise defeat an entire chassis.
• I check common-cause points such as connectors, airflow, firmware images, and maintenance actions before claiming N+1 or dual-path availability.

I keep high-speed signal returns continuous through the interconnect and treat chassis bonding and power return as deliberate current paths, not grounds to join arbitrarily.

• Differential and single-ended signals get adjacent ground pins at connectors so return current does not detour through mounting hardware or another cable.
• I do not split a high-speed reference plane; any layer or board transition gets a nearby ground return path with low inductance.
• Cable shields bond to chassis with a short, low-impedance connection at entry, preferably a full-perimeter termination, instead of carrying shield current through digital ground.
• The chassis-to-circuit connection is chosen from safety, ESD, and emissions needs, with mounting points controlled so accidental extra bonds do not form unpredictable loops.

I prevent differential energy from becoming common mode by preserving symmetry and return continuity before adding filters.

• Connector pinout, pair breakout, via geometry, and reference transitions are kept symmetric because mode conversion at those points often dominates cable radiation.
• External cable shields terminate to chassis at the entry with low transfer impedance, while unshielded interfaces get a defined common-mode return path at the connector.
• Common-mode chokes are added only after checking saturation, differential insertion loss, and the actual offending frequency because they can move a resonance or damage the eye.
• I validate the architecture with mixed-mode S-parameters and current-probe or near-field measurements on representative cables before formal emissions testing.

I co-design board partitioning with the enclosure and airflow from the start because connector position and heat removal can make an electrically clean split unusable.

• High-dissipation parts follow the actual airflow and mechanical heatsink load path, with fin, fastener, tolerance and assembly-tool keepouts represented in the ECAD model.
• Connector choice accounts for mating force, misalignment allowance, cycle life, card guides, bend radius and tolerance stack rather than only pin count and bandwidth.
• Low-margin or serviceable parts stay out of exhaust hot spots and remain reachable without removing unrelated boards.
• I check fan failure, dust loading, card extraction, cable routing and human access while ECAD and MCAD changes are still affordable.

I use cascaded, renormalized multiport S-parameters to model the complete differential path and compare it with the protocol's channel metric, not just an insertion-loss mask.

• Sdd21 shows differential insertion loss, Sdd11 and Sdd22 expose reflections, and mixed-mode terms such as Scd21 reveal energy converted to common mode.
• I verify reference impedance, port order, frequency range, passivity, and causality before trusting a vendor model or measurement.
• Package, launches, vias, connectors, traces, and any cable are cascaded in physical order, with fixtures de-embedded to the defined compliance planes.
• I inspect resonances and insertion-loss deviation, then run COM or the protocol-specific statistical eye calculation because equal loss curves can produce different link margin.

I treat electrical compliance as a necessary boundary check and specify end-to-end interoperability separately for the intended transmitters, channels and receivers.

• The BER target includes the protocol-defined error level, a test duration or bit count that supports the required confidence, and limits for corrected errors or retries that could hide a weak raw channel.
• Receiver tolerance, transmitter amplitude and jitter, equalizer training and stressed-input behavior are evaluated at the same defined compliance planes.
• Qualification spans process, voltage and temperature corners plus allowed equalizer settings so a link has margin beyond one nominal operating point.
• Release criteria cover representative vendor combinations and quantified margin beyond the compliance limit rather than a single open-eye capture.

I tune transmitter FFE and receiver CTLE or DFE together against the measured channel, using only enough equalization to recover margin.

• Transmitter pre-emphasis compensates predictable high-frequency loss but consumes swing and can increase crosstalk and emissions, so maximum tap values are rarely the best setting.
• CTLE restores high-frequency content but also amplifies noise, while DFE removes post-cursor ISI without boosting noise but can propagate decision errors.
• I use channel simulation to narrow the tap space, then confirm training behavior and BER across process, voltage, temperature, and representative endpoints.
• If the optimum sits at an equalizer limit, I treat that as a channel-architecture problem rather than signing off a fragile preset.

I use a redriver for a moderately lossy channel that still has acceptable jitter, and a retimer when the link needs a new clock and data boundary.

• A redriver is lower power, latency, and cost, but its linear equalization cannot remove accumulated jitter or repair a fundamentally closed input eye.
• A retimer recovers clock and data and splits one long channel into two compliant segments, but it adds protocol dependence, reference-clock constraints, firmware, heat, and interoperability work.
• I place a redriver after the dominant loss while preserving enough output reach, whereas a retimer is placed so both surrounding segments independently meet its input and output budgets.
• I decide from segment S-parameters, jitter tolerance, training behavior, power states, and fault recovery rather than from total trace length alone.

I set a victim-noise budget at the receiver and allocate it to connector coupling, via coupling, routing, and differential-to-common-mode conversion.

• I examine worst neighboring lane assignments and aggregate simultaneously active aggressors with their realistic correlation rather than quoting one pair's NEXT value.
• Ground pins, pair spacing, short breakout regions, symmetric antipads, and backdrilled or blind vias reduce coupling and remove resonant stubs at the source.
• Mixed-mode S-parameters expose Scd and Sdc conversion that ordinary differential insertion loss misses, especially through asymmetric connector launches.
• I simulate the full pin field and validate a representative coupon because an isolated vendor pair model can omit the dominant adjacent rows and vias.

I close setup and hold at the receiver for both timing extremes, including the data path, forwarded clock path, and every source of relative uncertainty.

• The budget includes transmitter clock-to-out, package skew, PCB mismatch, receiver setup and hold, duty-cycle distortion, jitter, and process, voltage, and temperature variation.
• I use min and max flight times, not nominal length matching, because package escape and different reference layers can dominate the visible PCB lengths.
• Clock centering or a DLL can move the sampling point, but its range, step size, and added jitter remain part of the budget.
• Constraints come from the remaining timing window and are verified with post-layout extraction and IBIS simulation, then correlated at the receiver pins where practical.

I use a common reference when it can be distributed with clean, bounded skew, and independent references when modularity or fault isolation matters more.

• A common reference simplifies frequency-offset compensation and often reduces elastic-buffer requirements, but the fanout tree becomes a shared reach and noise dependency.
• Independent references support hot-plug and separately powered cards, but the protocol must provide frequency compensation, asynchronous buffering or a defined architecture such as SRIS.
• SSC behavior, ppm tolerance, retimers and clock-recovery limits must satisfy the protocol-specific common-clock, SRNS or SRIS rules; they cannot be inferred from the connector alone.
• I include startup, missing-clock behavior and card removal in the decision because an architecture that works only in steady state is incomplete.

I start from the receiver's allowed jitter and work backward through the clock transfer functions instead of adding every data-sheet RMS number.

• Oscillator phase noise is integrated over the protocol-specified band, while PLL bandwidth determines which reference noise passes and where VCO noise dominates.
• Uncorrelated oscillator, PLL, fanout, and supply-induced terms combine by root-sum-square, but correlated spurs and deterministic jitter are kept explicit.
• Each fanout branch gets additive jitter, skew, signal-integrity, and load limits, with unused outputs and termination handled as the vendor specifies.
• I verify the final clock at the consumer with phase-noise or jitter measurements using the same bandwidth and filtering assumptions as the requirement.

I treat SerDes and clock rails as part of the timing path and budget supply-noise conversion into jitter alongside channel loss.

• I combine the vendor-provided or measured supply-pushing transfer function in phase or jitter per volt with the simulated rail-noise spectrum; I use PSRR only when its relationship to the relevant timing path is explicitly defined.
• Package and board impedance are modeled with the regulator, decoupling and dynamic load so antiresonances are visible rather than hidden by capacitor count.
• A sensitive rail may need a dedicated regulator or damped filter, but I avoid a ferrite that creates a high-Q peak or violates the transient requirement.
• For correlation, I stress major consumers while measuring rail spectrum, clock phase noise and link errors together, which separates supply coupling from trace loss.

I define a manufacturable stackup family with common impedance rules while allowing each board to change thickness or layer count without changing interface behavior.

• Every high-speed layer has a continuous adjacent reference plane; layer transitions use a nearby stitching via when both references are the same ground, while different reference potentials require an engineered low-inductance return path such as an appropriate stitching capacitor.
• Targets such as 50 ohms single-ended or 85 and 100 ohms differential come from the interface specification rather than a platform-wide preference.
• For the fastest channels, I include copper roughness, glass weave, resin content, plating and fabrication tolerance in the field-solver limits.
• Board and backplane vendors build controlled-impedance coupons, and connector transitions are tuned to the actual finished stackups rather than a generic trace geometry.