FPGA Engineer interview questions

I partition around data ownership, clock boundaries, and physical locality rather than around an arbitrary module size.

• Each partition gets an explicit contract for throughput, latency, ordering, reset behavior, and backpressure.
• High-bandwidth producer and consumer logic stay together so wide buses do not cross congested regions unnecessarily.
• I leave registers or asynchronous FIFOs at boundaries so partitions can close timing and be verified independently.

A scalable hierarchy exposes stable transaction-level interfaces while keeping implementation choices local to each subsystem.

• Control, payload, and status use typed or consistently packaged interfaces instead of loose signal bundles.
• Parameters express supported architectural variants, while illegal combinations fail during elaboration rather than creating fragile generate logic.
• The synthesis hierarchy follows useful physical and verification boundaries, but trivial wrappers are flattened to avoid blocking optimization.

I use partial reconfiguration only when changing one region at runtime creates enough value to justify fixed boundaries and a harder verification problem.

• Good fits include mutually exclusive accelerators or field updates where the static control and I/O plane must remain active.
• The reconfigurable partition needs a stable interface, isolation during loading, and reserved resources and routing in the floorplan.
• I avoid it when a normal mode mux fits, because reconfiguration time, bitstream management, and state restoration add system complexity.

I choose from the required access pattern and elasticity, not from interface preference.

• Streaming gives low latency and natural backpressure when data is consumed in order and each stage can sustain the target rate.
• Memory buffering absorbs burst mismatch and enables random access or reordering, but it adds arbitration, capacity planning, and round-trip latency.
• Hybrid designs usually stream the steady-state path and use bounded buffers only at rate changes or scheduling boundaries.

I treat clock domains as explicit architectural regions and minimize both their number and the signals crossing between them.

• Related functions share a clock when power and timing allow, while interfaces to transceivers, memory, and processors keep their required clocks.
• Crossings use a small set of approved primitives for levels, events, bundled data, and asynchronous streams.
• Frequency plans, reset dependencies, and clock availability are captured with each interface before RTL integration begins.

The reset architecture must define ownership, sequencing, and recovery semantics for every clock domain.

• Assertion may be asynchronous when hardware requires it, but deassertion is synchronized independently in each active domain.
• Datapath registers without architectural state can often avoid reset, reducing routing and preserving BRAM, DSP, and retiming inference.
• Interfaces remain isolated until clocks are stable and both sides have reached a protocol-safe state.

I floorplan only where device topology or repeated implementation evidence gives a clear physical reason.

• Hard endpoints such as GTs, DDR I/O, PCIe blocks, and memory columns usually anchor the nearby logic first.
• Wide, high-rate pipelines benefit from compact regions, while unrelated control logic should not consume scarce local routing.
• Regions need enough whitespace for placement and routing, because a tight pblock can turn locality into congestion.

I treat an SLR boundary as a scarce, higher-delay communication boundary rather than as ordinary fabric.

• Bandwidth-heavy blocks are partitioned so most traffic stays inside one SLR near their hard IP and memory resources.
• Unavoidable crossings are registered, width-limited, and spread across dedicated crossing resources instead of carrying deep combinational logic.
• The latency contract includes the crossing stages, which prevents later timing fixes from changing system behavior unexpectedly.

I keep functional RTL portable and isolate physical intent behind narrow technology-aware wrappers and architectural choices.

• Wrappers cover hard primitives such as GTs, clock buffers, DSP cascades, and specialized memories with a vendor-neutral contract above them.
• Pipeline placement, banking, and data width reflect device topology even when the arithmetic behavior remains generic.
• Synthesis attributes are localized and checked in reports, because an ignored attribute must not silently become part of correctness.

I start with the external latency limit and allocate cycles to interfaces, transport, buffering, and computation before blocks are implemented.

• Fixed-latency stages get cycle contracts, while elastic stages get bounded occupancy and backpressure assumptions.
• Clock-domain crossings and SLR crossings are budgeted explicitly because their synchronization or register stages are not optional.
• I preserve a small architectural reserve so timing closure does not require violating the top-level interface contract.

I separate the transceiver wrapper, lane adaptation, alignment, and protocol layers so each has one timing and verification contract.

• Every lane handles encoding, gearbox width, elastic buffering, and local status before data enters shared bonding logic.
• Deskew markers and bounded per-lane FIFOs align lanes without coupling recovered clocks directly into the core pipeline.
• The shared layer exposes lane degradation and reconfiguration policy instead of hiding a failed lane as corrupted payload.

The reference-clock plan is driven by transceiver quad topology, protocol jitter limits, and which links must operate independently.

• Lanes sharing a PLL must have compatible rates and reset behavior, while unrelated standards may need separate QPLL or CPLL resources.
• Board clock quality and the vendor jitter mask matter because a clean nominal frequency does not guarantee receiver margin.
• Core logic crosses from recovered or user clocks through defined elastic boundaries rather than assuming phase relationships.

I choose the parallel width and user clock together to meet line throughput with timing margin and manageable routing.

• A wider datapath lowers fabric frequency but increases mux width, gearbox cost, and congestion around the transceiver.
• A narrower datapath simplifies routing width but can force a clock rate that ordinary fabric cannot close reliably.
• Encoding and protocol overhead are included in the calculation, so line rate is never treated as payload bandwidth.

The key decisions are transaction segmentation, buffering, ordering, and where the PCIe clock domain ends.

• Request and completion paths need separate queues sized for maximum payload, outstanding tags, and downstream backpressure.
• A DMA layer converts descriptors into bounded AXI transactions while keeping completion and error handling independent from payload movement.
• Clock crossing and reset containment sit next to the PCIe hard block so the application fabric sees a stable internal contract.

PCIe credits and ordering rules determine how much concurrency is safe and where buffering must exist.

• Posted, non-posted, and completion traffic use separate credit pools, so one blocked class should not deadlock the others.
• Tags set the number of outstanding reads, but useful concurrency also depends on completion latency and reorder capacity.
• Relaxed ordering can improve throughput only when the application contract permits responses to become visible out of order.

I keep frame semantics in the MAC, code-group and lane semantics in the PCS, and serial electrical adaptation in the PMA.

• The MAC handles framing, FCS, inter-packet behavior, and flow-control frames without depending on transceiver details.
• The PCS handles encoding, alignment, block lock, and lane distribution for the selected Ethernet standard.
• The PMA and GT wrapper own serialization, clock recovery, equalization, and the physical lane interface.

I place buffering at rate-change and scheduling boundaries, not after every protocol layer.

• Small elastic FIFOs absorb clock tolerance between MAC and application domains without masking sustained overload.
• Shared packet memory improves utilization across ports, but it needs admission control so one flow cannot consume all capacity.
• Cut-through forwarding lowers latency, while store-and-forward enables full-frame checks and requires space for the largest supported frame.

I capture timestamps at a fixed physical pipeline point and carry them as metadata beside the frame.

• The timestamp clock uses a disciplined time counter whose frequency adjustment does not create discontinuous time steps.
• TX and RX insertion points have characterized fixed latency, while variable queueing is kept outside the correction boundary.
• Clock-domain transfer preserves the timestamp atomically, usually through a FIFO rather than independent bit synchronization.

The wrapper must turn application traffic into controller-friendly bursts while containing calibration, clocking, and reset details.

• Request queues separate reads and writes and expose enough outstanding work for the controller scheduler to hide bank timing.
• Width conversion, alignment, and ECC handling sit at a defined boundary so clients do not depend on the native PHY width.
• Initialization and calibration gate traffic explicitly, and failures become architectural status rather than an unqualified ready signal.

I improve effective bandwidth by presenting long, aligned, bank-friendly traffic and by avoiding direction changes.

• Per-client queues combine adjacent accesses into bursts and keep enough requests outstanding to cover command and refresh gaps.
• Read and write batching reduces bus turnaround cost, but the scheduler bounds batching so latency-sensitive traffic is not starved.
• Data layout distributes hot streams across banks or channels instead of sending every client to the same address region.