FPGA Engineer interview questions

Setup slack is the required arrival time at the destination register minus the actual data arrival time.

• Data arrival includes launch-clock delay, clock-to-Q delay, combinational delay, and routing delay from the source register.
• Required time comes from the destination capture edge, capture-clock delay, setup time, and any setup uncertainty.
• Positive slack means the path meets the modeled requirement, while negative slack gives the amount by which it misses.
• The check must pass for every analyzed setup corner and clock relationship, not only the nominal clock period.

Clock period changes the next-edge setup requirement but normally does not change the same-edge hold requirement.

• A longer period gives maximum-delay data more time to reach the destination before its setup deadline.
• Hold analysis uses the earliest data arrival after the relevant capture edge, so another cycle of period is not added to that check.
• Hold slack is earliest arrival minus required hold time, including minimum clock-path delay and skew.
• A real hold repair adds minimum data delay or changes placement and routing rather than lowering frequency.

WNS describes the single worst slack, while TNS sums the negative slack across all failing endpoints in a path group.

• WNS of -0.20 ns means at least one endpoint misses its requirement by 0.20 ns.
• TNS distinguishes one isolated failure from many smaller failures that may require a broader architectural change.
• The number of failing endpoints adds context because equal TNS values can represent very different violation distributions.
• Setup and hold reports have separate WNS and TNS values and must be reviewed independently.

The critical path is the constrained path with the lowest slack, not necessarily the one with the most logic levels.

• A short path with long programmable routing or high fanout can be slower than a deeper path using local dedicated connections.
• Carry chains and DSP cascades can traverse several operations faster than equivalent logic mapped through general LUT routing.
• Clock skew, uncertainty, and the endpoint relationship affect slack even when two data paths have equal delay.
• Criticality can change after placement and routing because physical delay is only estimated during synthesis.

Clock skew models different launch and capture arrival times, while uncertainty reserves margin for effects such as jitter and phase error.

• Later capture-clock arrival relative to launch generally helps setup slack because data gets more time.
• The same positive skew generally hurts hold slack because old data must remain stable longer at the destination.
• Setup uncertainty reduces the available maximum-delay window, and hold uncertainty increases the required minimum-delay margin.
• Tool-generated clock propagation and explicit uncertainty must be modeled consistently to avoid hiding or double-counting margin.

A generated-clock constraint preserves the frequency, phase, and source relationship between the derived clock and its master clock.

• The constraint identifies the actual generation pin and expresses division, multiplication, phase shift, or edge mapping.
• Static timing can then analyze crossings between related domains with the correct launch and capture edges.
• Declaring the output as an unrelated primary clock loses that relationship and can create incorrect checks or unnecessary CDC exceptions.
• Each physically used PLL or clock-divider output needs its own generated-clock definition unless the FPGA tool derives it automatically.

I/O delay constraints model timing outside the FPGA relative to the clock that governs the interface.

• Maximum input delay includes the source device's latest clock-to-out plus board delay before the FPGA input.
• Minimum input delay models the earliest arrival and is required for a meaningful input hold check.
• Maximum output delay represents the receiver's setup requirement plus board delay, while minimum output delay captures its hold requirement.
• A virtual clock is useful when the external reference clock is not distributed through the FPGA fabric.

A multicycle constraint states that a functionally valid synchronous transfer is allowed more than the default number of clock edges.

• A setup multicycle of N moves the setup capture edge out to the Nth applicable edge without adding any hardware.
• The corresponding hold relationship usually needs an N minus 1 adjustment so the tool does not enforce hold against the shifted edge.
• A clock enable or protocol condition must guarantee that the destination does not consume intermediate data early.
• The exception should target only the intended registers because a broad multicycle can hide ordinary single-cycle failures.

A false path removes timing analysis only where no functional launch-to-capture timing requirement exists.

• A targeted false path suits a specific nonfunctional path or the intended first stage of a recognized synchronizer.
• Asynchronous clock groups cut timing in both directions between whole clock sets and are therefore much broader.
• Neither exception makes a CDC transfer safe, so synchronizers, handshakes, or asynchronous FIFOs remain necessary.
• A slow but functionally sampled synchronous path is not false merely because it rarely changes.

Explicit maximum or minimum delay constraints are used when the path needs a bounded data delay that the default edge relationship does not express.

• A maximum delay can bound a source-synchronous path or limit skew among independently synchronized Gray-code bits.
• A minimum delay can preserve contamination delay where data must not reach the destination too early.
• The datapath-only option excludes clock skew from the bound when the requirement is specifically about data-path delay.
• These constraints must remain scoped to named endpoints because they override ordinary timing assumptions.

Setup is dominated by late data arrival, while hold is dominated by early data arrival, so their worst process, voltage, and temperature conditions differ.

• Slow logic and routing tend to worsen maximum-delay setup checks.
• Fast logic and routing tend to worsen minimum-delay hold checks.
• Clock networks can scale differently from data paths, so on-chip variation and skew can move the true worst corner.
• Passing one nominal corner does not establish closure unless every required setup and hold analysis view passes.

Register retiming moves sequential boundaries across combinational logic to rebalance path delay while preserving external cycle behavior.

• Moving a register through equivalent logic can shorten one stage without changing the number of interface cycles.
• Asynchronous resets, incompatible enables, dont_touch constraints, and certain memory or DSP boundaries can block legal movement.
• Retiming may change internal register names and observation points even when the block's input-to-output behavior is preserved.
• Equivalence checking or a latency-aware regression should confirm that the transformed design still satisfies the contract.

Boolean simplification may not help when routing, fanout, or placement dominates the path delay.

• A high-fanout control net can spend more time in programmable interconnect than in the destination LUTs.
• Congested placement can force detours between otherwise simple logic levels.
• Register duplication can localize a control signal at the cost of extra flip-flops and replicated logic.
• A pipeline boundary or floorplan change can be more effective when the report shows routing rather than cell delay as dominant.

Synchronizer MTBF grows exponentially with available resolution time and falls as source activity and destination clock rate increase.

• A transition inside the receiving flip-flop's aperture can leave its output metastable for an unpredictable interval.
• Each additional destination-clock stage gives the metastable node roughly another cycle to settle before observation.
• Faster destination clocks and more frequent asynchronous transitions create more opportunities for a metastable sample.
• Device-specific metastability constants and actual routing delay are needed for a numeric MTBF estimate.

A correct level synchronizer is a destination-clocked register chain whose first stage has no functional fanout.

• Only the final stage feeds destination logic because the first stage has the highest probability of unresolved metastability.
• No combinational logic belongs between the stages, and implementation attributes should identify them as synchronizer registers.
• Close placement maximizes metastability resolution time by minimizing routing delay between stages.
• The source level must remain stable long enough to be sampled, so this structure alone does not guarantee capture of a short pulse.

Registering the source removes combinational glitches that would otherwise increase asynchronous transition activity at the synchronizer input.

• A combinational expression can toggle several times as its inputs settle even when its final logical value changes once.
• Every extra transition increases the opportunity for a destination edge to sample inside the metastability aperture.
• A source register also makes the crossing's origin and stability contract explicit to CDC analysis.
• This step does not replace the destination synchronizer because the registered source remains asynchronous to that clock.

A request-acknowledge handshake transfers ownership by holding data stable until both domains observe the control exchange.

• The source registers the payload, asserts request, and keeps both unchanged until a synchronized acknowledge returns.
• The destination synchronizes request, captures the stable payload, and asserts acknowledge in its own clock domain.
• The source synchronizes acknowledge back before clearing request or changing the payload.
• The round trip costs several clock cycles but provides lossless transfer and natural backpressure.

A toggle synchronizer encodes each source event as a state change that persists until the destination samples it.

• The source flips one bit for every accepted event instead of sending a one-cycle pulse.
• The destination synchronizes that bit and XORs the stable sample with a delayed copy to recreate a local one-cycle pulse.
• Consecutive events must be separated enough for each toggle value to cross, or two changes can cancel before observation.
• Both domains need compatible reset states because a reset mismatch can appear as a false event.

The choice depends on whether event spacing is bounded and whether loss or backpressure is acceptable.

• Pulse stretching is simplest when a known minimum width spans multiple destination edges, but nearby events can merge.
• A toggle transfers sparse events without a return path, provided the source cannot toggle twice before destination observation.
• A handshake guarantees each accepted event and tells the source when another can be sent, at the cost of round-trip latency.
• None of these schemes should be selected from average clock rates alone because relative phase and worst-case spacing control capture.

Bundled-data CDC keeps a multibit payload stable while a separately synchronized control signal announces when it may be captured.

• The source registers data before asserting request or valid.
• Synchronizer latency gives the data bus time to settle through its direct source-to-destination paths.
• The destination captures the entire bus only after observing the synchronized control event.
• The source must not change the bus until an acknowledge or a specified hold interval completes.