FPGA Engineer interview questions

An FPGA is a reconfigurable chip whose hardware structure is programmed for a particular digital circuit.

• A CPU executes a sequence of instructions on mostly fixed hardware, while an FPGA can implement many operations as parallel circuits.
• An ASIC has fixed circuitry after fabrication and can offer better density or efficiency, but an FPGA can be reprogrammed after manufacturing.
• An FPGA design maps logic into resources such as LUTs, flip-flops, memories, DSP blocks, and routing.

A configuration bitstream programs the FPGA resources and their connections to implement a synthesized design.

• Configuration bits select LUT contents, routing switches, I/O behavior, and options inside hard blocks.
• The file is generated for a specific FPGA family and device, so it is not portable machine code.
• Many SRAM-based FPGAs load the bitstream from external flash or a host each time power is applied.

An HDL describes hardware structure and behavior that operate concurrently rather than a sequence of processor instructions.

• Separate always blocks or VHDL processes represent logic active at the same time, even though statements inside one procedural block have defined semantics.
• Signal widths, clocks, registers, and combinational paths affect the resulting circuit directly.
• Synthesizable HDL must map to available hardware, while a simulator can execute additional verification-only constructs.

A Verilog module defines a reusable hardware block with an interface made of input, output, and inout ports.

• Input ports carry signals into the block, while output ports expose values produced inside it.
• Port widths such as logic [7:0] data make the number of physical signal bits explicit.
• Instantiating a module creates hardware for that block and connects its ports to signals in the parent module.

Combinational logic is commonly described with assign statements or an always_comb block that assigns every output on every path.

• An assign statement suits a direct expression such as assign sum = a + b.
• always_comb automatically reacts to signals read by the block and allows procedural if or case logic.
• Every assigned variable needs a value for all input combinations, often through a default assignment, to avoid a latch.

Clocked sequential logic is normally described in an always_ff block triggered by a clock edge.

• always_ff @(posedge clk) models flip-flops that sample their next values on the rising edge.
• Non-blocking assignments preserve the simultaneous update behavior expected from a bank of registers.
• A reset or clock enable belongs inside the block when those controls are part of the intended register behavior.

A continuous assignment drives a net from an expression continuously, while a procedural assignment executes inside an always or initial block.

• assign y = a & b updates y whenever an operand changes and directly represents combinational logic.
• Procedural assignments support control flow such as if and case and usually target variables declared as logic in SystemVerilog.
• A signal should normally have one clear driver, because multiple procedural drivers are not ordinary synthesizable register behavior.

A blocking assignment takes effect immediately within its procedural sequence, while a non-blocking assignment schedules the update for the end of the current simulation step.

• Blocking = is the usual choice for temporary calculations and outputs in combinational always_comb blocks.
• Non-blocking <= is the usual choice for registers in edge-triggered always_ff blocks.
• Using non-blocking assignments for q1 <= d and q2 <= q1 makes q2 receive the previous q1 value, matching two cascaded flip-flops.

A latch is inferred when combinational procedural logic leaves an output unassigned for some input condition, forcing it to retain its previous value.

• An if without an else can infer a latch when the block assigns the output only in the true branch.
• Assigning a default value before the conditional covers the missing paths without repeating every assignment.
• A latch is level-sensitive storage and is usually unintended in synchronous FPGA RTL.

always_comb automatically includes dependencies read by the block and states the designer's combinational intent.

• A manual list such as always @(a or b) can become stale when the expression later starts reading c.
• A missing sensitivity signal can make RTL simulation disagree with the synthesized combinational circuit.
• Tools can apply extra checks to always_comb, including restrictions on how its assigned variables are driven elsewhere.

wire represents a net driven by a continuous source, while logic is a variable type suitable for most single-driver RTL signals.

• A module output or assign statement can drive a wire because the net reflects its driver's value.
• An always_comb or always_ff block assigns a logic variable procedurally.
• Declaring a signal as logic does not create a flip-flop by itself, because the surrounding assignment and control structure determine the hardware.

Parameters let one RTL module be configured at elaboration time without duplicating its implementation.

• A WIDTH parameter can define port widths, register sizes, and loop bounds consistently.
• Each module instance can override the default parameter with a constant value.
• Parameters describe static hardware choices and do not behave like writable registers during operation.

Signal width and signedness determine how operands are extended, how arithmetic is interpreted, and which result bits are retained.

• Adding two unsigned 8-bit values may need a 9-bit destination to preserve a carry result up to 510.
• A signed value uses its top bit as the sign and is sign-extended, while an unsigned value is normally zero-extended.
• Explicit sizes and casts prevent unsized literals or mixed signed operands from producing surprising comparisons and arithmetic.

Verilog simulation uses 0 and 1 for known logic levels, X for an unknown value, and Z for high impedance.

• X can appear from an uninitialized register, conflicting drivers, or an operation whose result cannot be determined.
• Z models a released tri-state connection, which is mainly meaningful at FPGA I/O pins rather than ordinary internal fabric.
• Inspecting X values helps expose missing reset or assignment logic instead of masking the problem with a forced zero.

Bitwise operators act on corresponding bits, logical operators produce a truth value, and reduction operators combine all bits of one vector.

• For 4'b1010 and 4'b1100, bitwise & produces 4'b1000.
• Logical && treats each whole operand as false or true and returns a one-bit result.
• Reduction &data returns one only when every bit of data is one, while reduction |data detects any set bit.

Concatenation, replication, and part-selects assemble or extract explicit groups of vector bits.

• {header, payload} places the header bits above the payload bits in one wider vector.
• {4{bit_value}} repeats one value four times and is useful for masks or explicit extension.
• data[7:4] selects a four-bit slice, so declared index direction and boundary positions must be checked carefully.

Both statements can describe multiplexing, but an if chain naturally expresses priority while case selects among explicit values of one expression.

• In if a then else if b, a wins when both conditions are true, so synthesis builds priority behavior.
• A case statement is clear for an opcode or FSM state with mutually exclusive encoded choices.
• A default branch or an assignment before the statement covers unmatched values and prevents unintended storage.

A VHDL entity declares a block's external interface, while an architecture defines one implementation of that interface.

• The entity lists ports with directions such as in, out, and inout and types such as std_logic_vector.
• The architecture contains concurrent assignments, processes, component instances, and internal signals.
• Keeping interface and implementation separate allows more than one architecture to be associated with the same entity.

A VHDL signal represents communication between concurrent logic, while a variable updates immediately within the process or subprogram that owns it.

• A signal assignment with <= schedules a new value, so reads later in the same process may still see the old signal value.
• A variable assignment with := takes effect immediately for following statements in that process activation.
• Variables are useful for intermediate calculations, but the process structure still determines whether synthesis creates combinational logic or registers.

A VHDL process describes either combinational or clocked behavior through its sensitivity and assignment structure.

• A combinational process reads all relevant inputs and assigns every output on every path, with process(all) available in VHDL-2008.
• A clocked process commonly uses rising_edge(clk) and updates signals that synthesize into flip-flops.
• Concurrent processes execute independently, so their source-code order does not serialize the hardware blocks.