Interviewfragen: Hardware Engineer

Characteristic impedance is the ratio of a traveling wave's voltage to current, set by distributed inductance and capacitance rather than DC resistance.

• Trace width, copper thickness, distance to the reference plane, and dielectric constant define the field geometry and therefore Z0.
• A wider trace or a smaller plane distance usually adds capacitance and lowers Z0, while a narrower trace or larger distance raises it.
• Higher dielectric constant also lowers Z0, and finished copper shape matters because etching changes the trace sidewalls and width.
• I use the fabricator's actual stackup and tolerances in a field solver instead of relying on a generic impedance calculator.

The load reflection coefficient is Γ = (ZL - Z0) / (ZL + Z0), so it gives the reflected voltage as a fraction of the incident wave.

• A matched load has Γ = 0, an open has Γ = +1, and a short has Γ = -1.
• A 50 Ω line terminated in 75 Ω has Γ = 0.2, so 20% of the incident voltage reflects with the same polarity.
• The reflected wave can cause overshoot, undershoot, or multiple settling steps, with severity set by both the mismatch and the edge bandwidth.

I treat an interconnect as a transmission line when its one-way flight time is no longer small compared with the signal rise or fall time.

• The fastest edge matters, not the clock frequency, because that edge contains the high-frequency energy that sees distributed behavior.
• A useful conservative screen is tflight ≥ tr / 6; below that, lumped analysis is more likely to be adequate.
• At roughly 150 ps/in, a 1 ns edge reaches that threshold at about 1.1 in of route.
• The rule is a screening estimate, so connectors, vias, loads, and strict noise margin can justify transmission-line analysis on a shorter path.

Source series termination makes the driver impedance plus a resistor approximately equal to the line impedance so the returning reflection is absorbed at the source.

• I place the resistor next to the driver and choose Rseries so Rdriver + Rseries ≈ Z0.
• With a high-impedance receiver, the source launches about half the final amplitude; when the wave first reaches the load, ΓL ≈ +1 doubles the load voltage to its final value.
• It consumes almost no static power and works well for a point-to-point, unidirectional net with one receiver.
• It is a poor fit for distributed loads because intermediate taps can see the half-amplitude step before the reflection completes the transition.

Both terminate at the receiver, but parallel termination uses one resistor to a rail while Thevenin termination uses a divider to set both impedance and bias voltage.

• A parallel resistor near the load is chosen near Z0 and absorbs the incident wave immediately, but one logic state can draw substantial DC current.
• For Thevenin termination, Rtop || Rbottom should equal Z0 and the divider ratio sets the idle voltage seen by the line.
• Thevenin termination can suit interfaces that need a defined bias, but it costs two parts and draws divider current even when the signal is static.
• Both need a low-impedance termination rail and tight placement at the receiver, or the connection to the resistor becomes another stub.

A differential pair is normally terminated with a resistor across the two conductors equal to the pair's differential impedance.

• A 100 Ω pair therefore gets a 100 Ω resistor at the receiver, placed close enough that the pads and connecting traces do not form a meaningful stub.
• The resistor absorbs the differential, or odd-mode, wave without creating a DC path from either conductor to ground.
• A split termination can use two 50 Ω resistors with a filtered midpoint to control common-mode energy, but its extra pads and imbalance must be included in the channel design.

Propagation delay is the wave's travel time, while electrical length expresses that same delay as phase at a particular frequency.

• A first-order delay is td = length × √εeff / c, with εeff set by the stackup and field distribution.
• Electrical length is θ = 2πf td, so the same physical trace is electrically longer at higher frequency.
• Two equal physical lengths can have different delays when they use different layers or dielectrics, so timing constraints should ultimately be expressed in time.

I derive a board skew budget from the receiver timing window and convert only that remaining time into a length tolerance.

• The budget includes transmitter skew, package mismatch, connector delay, jitter, setup and hold margin, and the PCB contribution.
• If 20 ps remains for the board and the route delay is 150 ps/in, the corresponding mismatch limit is about 0.13 in, or 3.4 mm.
• I account for layer-dependent delay and pin-package length instead of assuming equal routed millimeters mean equal arrival time.
• Length tuning is kept only as tight as the budget requires because extra serpentine adds loss, coupling, and routing congestion.

Near-end crosstalk appears at the aggressor's launch end of the victim, while far-end crosstalk appears at the opposite end.

• NEXT comes from capacitive and inductive coupling components that add at the near end, and its pulse duration grows with the coupled section's round-trip delay.
• FEXT components partly oppose each other and arrive as a pulse at the far end whose amplitude depends strongly on edge rate and coupled length.
• In homogeneous stripline the far-end components can largely cancel, while microstrip's air-dielectric asymmetry leaves more residual FEXT.
• Closer spacing, longer parallel runs, and a more distant reference plane increase both forms of coupling.

Crosstalk is controlled by reducing shared fields, so spacing must be considered together with coupling length and distance to the reference plane.

• Increasing edge-to-edge spacing reduces coupling, while shortening parallel runs limits how long the aggressor can inject energy.
• Bringing a solid reference plane closer confines more field to that plane and can help more than adding the same absolute trace spacing.
• For equal-width traces, the 3W rule normally means three trace widths center-to-center, equivalent to a two-width edge-to-edge gap, but it ignores dielectric height, edge rate, layer type, and parallel length.
• I use spacing-to-plane-height ratios and field-solver or channel limits for critical nets rather than treating 3W as a guaranteed isolation value.

High-frequency return current follows the lowest-inductance path close beneath the signal, so a plane gap breaks the intended current loop.

• A continuous adjacent plane gives the return current a path that mirrors the trace and keeps loop area small.
• A slot or split forces the current around the opening, increasing loop inductance, radiation, and coupling into other circuits.
• The detour also changes the trace's local impedance because its field no longer sees the same reference geometry.
• I avoid routing fast signals across splits and treat a power plane as a valid reference only when its return path to the source is controlled through nearby decoupling.

A signal via is an impedance discontinuity, and its unused barrel can behave as an open-ended transmission-line stub.

• Via barrel inductance, pad capacitance, antipad size, and nearby return vias determine the transition impedance.
• The unused section reflects energy and can create a strong quarter-wave resonance when its electrical length becomes significant.
• Backdrilling removes the unused plated barrel from the far side while leaving a controlled residual stub above the connected layer.
• Blind or buried vias can avoid the stub, but backdrilling is often cheaper than advanced HDI and still adds fabrication tolerance and cost.

Differential and common-mode impedance come from different field patterns, so one cannot be inferred from a single-ended impedance value without the pair geometry.

• Differential excitation drives equal and opposite currents, concentrating much of the field between the conductors and using the odd mode.
• Common-mode excitation drives both conductors in the same direction, so current returns through the reference structure and uses the even mode.
• For a symmetric pair, Zdiff = 2Zodd, while the tied-pair common-mode port impedance is Zcm = Zeven / 2.
• A channel can meet 100 Ω differential impedance yet convert energy to common mode through skew, asymmetrical vias, or unequal reference geometry.

Intra-pair skew is delay mismatch between the positive and negative conductors of one pair, while inter-pair skew is arrival mismatch between separate pairs or lanes.

• Intra-pair skew converts differential energy into common mode, reduces the differential eye, and can increase emissions.
• Inter-pair skew affects alignment across lanes, but many serial protocols can tolerate or deskew more lane-to-lane delay than P-to-N delay.
• I therefore constrain P and N tightly through the same layers and transitions, then set lane-to-lane matching from the protocol's deskew budget.
• Blindly equalizing every lane can add unnecessary meanders and insertion loss without improving the receiver margin.

I choose AC coupling capacitors from the interface specification and the channel's low-frequency content, then place a matched part in each conductor at the specified end.

• The capacitor and termination form a high-pass response, so too little capacitance causes baseline droop during long runs of identical data.
• More capacitance is not free because a larger package can add ESL, pad capacitance, and a worse impedance discontinuity.
• Many interfaces assign the capacitors to the transmitter; both parts should be symmetric, close to each other, and present only once in the link.
• A small low-ESL package, compact pads, and suitable antipads keep the series transition from degrading the high-frequency channel.

DDR fly-by routing sends clock, command, and address signals sequentially past devices to avoid the large stubs of a passive star.

• The main route keeps controlled impedance and is terminated at its far end, but each device sees an intentional incremental flight-time delay.
• DDR training, including write leveling, compensates relevant timing offsets created by the fly-by arrival pattern.
• DQ and DQS are constrained per byte lane and rank, so their topology should not be copied blindly from the command and address bus.
• ODT switches termination inside the DRAM or controller for the active read, write, and rank state, reducing external parts and reflections from inactive loads.

DDR is source-synchronous, so each DQ bit is timed against the DQS strobe for its own byte lane rather than against a global clock alone.

• During writes the controller launches DQ and DQS, while during reads the DRAM launches them, so the budget must work in both directions.
• I match each DQ to its associated DQS within the controller and memory timing budget and keep the DQS P-to-N mismatch especially tight.
• Package delays, vias, connectors, and layer-dependent propagation count alongside visible PCB trace length.
• Different byte lanes need only meet their training and controller alignment limits, because excessive lane-to-lane tuning adds crosstalk and loss.

LVDS steers a nearly constant current between two conductors, and the receiver termination converts that current into a small differential voltage.

• A typical 3.5 mA current through 100 Ω produces a differential voltage magnitude of about 350 mV, or about 700 mV peak-to-peak between the two logic states.
• The low swing and opposite currents reduce switching noise and radiation compared with a large single-ended voltage swing.
• The 100 Ω resistor belongs across the pair at the receiver so the traveling wave sees its intended differential load.
• The receiver must still remain inside its common-mode input range because differential termination does not remove common-mode offsets.

Both use nominal 90 Ω differential routing, but USB 2.0 uses one bidirectional D+/D- pair while USB 3.x adds separate unidirectional SuperSpeed transmit and receive pairs.

• A USB 2.0 hub creates separate point-to-point segments; a passive star or long branch adds stubs and is not a valid substitute.
• SuperSpeed links are point-to-point and full duplex, with one TX pair and one RX pair in addition to the USB 2.0 pair.
• Pair symmetry, continuous references, and short connector or via discontinuities matter more as the SuperSpeed data rate rises.
• The 90 Ω target must use the fabricator's stackup, since copying a trace width between layers does not preserve impedance.

A PCIe lane is a full-duplex point-to-point channel made from one transmit pair and one receive pair.

• Link widths such as x1, x4, and x16 aggregate independent lanes rather than branching one differential pair to several receivers.
• Each pair follows the platform's controlled-impedance target, commonly 85 Ω differential, through connectors and layer transitions.
• The transmitter provides one matched series AC coupling capacitor in each TX conductor so the receiver can establish its own common-mode bias.
• PCIe receivers provide on-die termination, so adding an external far-end differential resistor would create the wrong load.